1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device which may stably transfer an electrical signal by forming a plurality of via holes and contact holes to an underlying conductive layer. According to the present invention, even though a contact hole or via hole is electrically shorted, it is possible to stably transfer electric signal through the other contact holes or via holes.
2. Description of the Background
Generally, with higher integration of semiconductor devices, a conductive line becomes narrower. The narrowing of the conductive line may cause an increase of resistance in the conductive line and a delay of signal transfer. To solve the problem of signal transfer delay, a multi-layered conductive line structure has been introduced instead of the existing single layered conductive line structure.
However, in the multi-layered conductive line structure, an interval between conductive lines is further decreased so that parasitic capacitance between conductive lines on the same layer is increased and signal transfer delay of the semiconductor device further deepens. Particularly, in case of a conductive line with finer line width, signal transfer delay by parasitic capacitance between conductive lines has a marked effect on operational features of semiconductor devices (such as signal transmission speed). To reduce parasitic capacitance between conductive lines, it is preferable to reduce the thickness of conductive line and to thicken a second insulating layer. Accordingly, many proposals have been provided, wherein the conductive line is formed of low specific resistance material, for example, copper presently used, and the second insulating layer is formed of low permittivity materials. However, in case of copper, since vapor pressure of etching by-products is low, it is difficult to perform a dry etching.
One solution to this problem involves a damascene process, which forms a copper conductive line by forming a via hole or contact hole through the second insulating layer, filling the via hole or contact hole with copper and planarizing the copper layer.
The copper conductive line adapted to the damascene structure has excellent electrical conductivity and low resistance compared with an aluminum or aluminum alloy conductive line, thus enabling finer conductive features and high integration of the conductive line while maintaining constant carrier current. The copper conductive line also has excellent electroplating characteristics, thus increasing reliability of the semiconductor device.
A dual damascene process is performed according to the following steps.
First, in a state where a lower conductive line is formed on a semiconductor substrate, a second insulating layer is formed on top of the substrate and the lower conductive line, and a certain portion of the second insulating layer is etched and removed as to expose the lower conductive line, thus forming a via hole and a trench. Then, a thin metal barrier is formed in the via hole and the trench in order to be in contact with the exposed lower conductive line, and a conductive layer, for example, a copper layer, is deposited to completely fill the via hole and the trench. Then, the copper layer is planarized with the second insulating layer, simultaneously forming a plug and an upper conductive line in the via hole and the trench.
Recently, as the design rules of semiconductor devices are refined, line widths of via holes and trenches are also narrowed. Thus, conductive layers such as the copper layer do not always completely fill the via hole and the trench, thus causing a problem in that a contact characteristic with the lower conductive line is degraded or the device fails as a result of an electrical short.
In the conventional damascene or dual damascene process, one via hole and one trench are formed for the plug and the upper conductive line. Thus, when the conductive layer does not completely fill the via hole and trench, an incomplete contact with the lower conductive line results, and a disconnection between the upper and lower conductive lines may be caused, degrading the electrical characteristics of the entire semiconductor device.
U.S. Pat. No. 5,918,149 (assigned to Advanced Micro Devices, Inc.), issued Jun. 29, 1999, discloses a method of improving an embedment property of the conductive layer in the via hole and trench. However, the method does not provide a fundamental solution for resolving the problem of degrading electrical characteristic due to the incomplete filling of the conductive layer.